quad e1 framer ic XRT84V24 preliminary rev. 1.0.1 1 general description the XRT84V24 quad e1 framer ic contains four in- dependent e1 framer blocks. each e1 framer block contains its own transmit and receive e1 framin function, transmit hdlc controller (which encapsu- lates contents of transmit hdlc buffers into lapd message frames) and receiver hdlc controller (which extracts payload content of receive lapd message frames from the incoming e1 data stream and writes it into the receive hdlc buffer). each framer also contains a transmit and overhead input port, which permits data link terminal equipment direct access to the outbound e1 frames and a re- ceive overhead output port, which permits data link terminal equipment direct access to the data link bits within the inbound e1 frames. features ? four independent, itu-t g.704 compliant trans- ceiver e1 framers ? supports channel associated signalin ? supports common-channel and primary rate isdn signalin ? supports fas, crc-multiframe and cas multi- frame framing stuctures ? contains two 96 byte transmit hdlc buffers and two 96 byte receive hdlc buffers for each channel ? contains microprocessor interface for popular types of microprocessors and supports pro- grammed i/o, burst and dma modes of read/write access ? each framer block can encode or decode the e frame data into/from the single-rail or dual-rail (ami or hdb3 encoded) formats ? detects and forces rai and ais alarms ? detects lof, cofa and los conditions ? each framer contains a 512 bit elastic store buffer ? uses a single +3.3v power supply ? available in either a 160 pin pqfp and 208 pin pqfp package applications ? sdh terminal or add/drop multiplexers supporting e1 framing ? e1 multiplexers ? channel service units (csus) ? lan routers with integrated e1 interfaces ? e1 frame relay interface ? isdn primary rate interfaces ? test equipment f igure 1. b lock d iagram of the XRT84V24 txpos_0 txneg_0 txlineclk_0 rxpos_0 rxneg_0 rxlineclk_0 microprosser interface block pcs_l pwr_l prd_l pd[7:0] pa[5:0] rxser_0 rxserclk_0 rxoh_0 rxohclk_0 txoh_0 txohclk_0 txser_0 txserclk_0 framer block 1 framer block 2 framer block 3 transmit e1 liu interface transmit e1 framer receive e1 framer hdlc controller transmit e1 overhead input interface transmit e1 serial input interface txlapd buffer rx lapd buffer receive e1 serial output interface receive e1 overhead output interface framer block 0 liu controller block gpo_6_cs_l_3 gpo_5_cs_l_2 gpo_4_cs_l_1 gpo_3_cs_l_0 gpo_2_sclk_l gpo_1_sdi gpo_0_sdo receive e1 liu interface
XRT84V24 quad e1 framer ic preliminary rev. 1.0.1 2 f igure 2. p in out of the XRT84V24 in the 160 pin pqfp package txchclk_3 txohclk_3 txoh_3 txmsync_3 txsync_3 gnd txserclk_3 txser_3 rxlos_3 rxohclk_3 rxoh_3 rxchclk_3 rxcasmsync_3 vdd rxcrcmsync_3 rxsync_3 rxserclk_3 rxser_3 tck tms tdi tdo gnd txser_2 txserclk_2 txsync_2 txmsync_2 txoh_2 txohclk_2 rxser_2 txchclk_2 rxserclk_2 vdd rxsync_2 rxcrcmsync2 rxcasmsync_2 rxchclk_2 rxoh_2 rxohclk_2 rxlos_2 nc pack_l_0 pblast_l vdd pack_l_1 pdata_0 preq_l_0 pdata_1 vdd preq_l_1 pdata_2 pint_l pdata_3 gnd pdata pdata_4 ptype_0 pdata_5 vdd ptype_1 pdata_6 ptype_2 pdata_7 gnd pdack_l paddr_0 pdben_l paddr_1 vdd pas_l paddr_2 pcs_l paddr_3 prd_l paddr_4 gnd pwr_l paddr_5 nc nc txchclk_0 txohclk_0 txoh_0 txmsync_0 txsync_0 gnd txserclk_0 txser_0 rxlos_0 rxohclk_0 rxoh_0 rxchclk_0 rxcasmsync_0 vdd rxcrcmsync_0 rxsync_0 rxserclk_0 rxser_0 oscclk reset_l 8khzref testmode gnd txser_1 txserclk_1 txsync_1 txmsync_1 txoh_1 txohclk_1 rxser_1 txchclk_1 rxserclk_1 vdd rxsync_1 rxcrcmsync_1 rxcasmsync_1 rxchclk_1 rxoh_1 rxohclk_1 rxlos_1 los_0 txpos_0 txneg_0 txlineclk_0 rxpos_0 rxneg_0 rxlineclk_0 los_1 gnd txpos_1 txneg_1 txlineclk_1 rxpos_1 rxneg_1 rxlineclk_1 vdd gpo_6_cs_l_3 gpo_5_cs_l_2 gpo_4_cs_l_1 gpo_3_cs_l_0 gpo_2_sclk gpo_1_sdi gpo_0_sdo vdd rxlineclk_2 rxneg_2 rxpos_2 txlineclk_2 txneg_2 txpos_2 gnd los_2 rxlineclk_3 rxneg_3 rxpos_3 txlineclk_3 txneg_3 txpos_3 los_3 nc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 160 lead pqfp
quad e1 framer ic XRT84V24 preliminary rev. 1.0.1 3 ordering information f igure 3. p in o ut of the XRT84V24 in the 20 pin pqfp package nc txchclk_3 txohclk_3 rxchn3_0 txoh_3 rxchn3_1 txmsync_3 rxchn_3_2 txsync_3 rxchn_3_3 vss txserclk_3 rxchn_3_4 txser_3 rxlos_3 rxohclk_3 rxoh_3 rxchclk_3 rxcasmsync_3 vdd rxcrcmsync_3 rxsync_3 rxserclk_3 rxser_3 tck tms tdi tdo gnd txser_2 txserclk_2 txsync_2 txmsync_2 txoh_2 txohclk_2 rxser_2 txchclk_2 rxserclk_2 vdd rxsync_2 txchn_2_4 rxcrcmsync2 txchn_2_3 rxcasmsync_2 rxchclk_2 txchn_2_2 rxoh_2 txchn_2_1 gnd rxohclk_2 txchn_2_0 rxlos_2 los_0 txpos_0 txchn_0_4 txneg_0 txchn_0_3 txlineclk_0 txchn_0_2 gnd rxpos_0 txchn_0_1 rxneg_0 txchn_0_0 rxlineclk_0 los_1 gnd txpos_1 txneg_1 txlineclk_1 rxpos_1 rxneg_1 rxlineclk_1 vdd gpo_6_cs_l_3 gpo_5_cs_l_2 gpo_4_cs_l_1 gpo_3_cs_l_0 gpo_2_sclk gpo_1_sdi gpo_0_sdo vdd rxlineclk_2 rxneg_2 rxpos_2 txlineclk_2 txneg_2 txpos_2 gnd los_2 rxlineclk_3 txchn_3_0 rxneg_3 txchn_3_1 rxpos_3 gnd txchn_3_2 txlineclk_3 txchn_3_3 txneg_3 txchn_3_4 txpos_3 los_3 nc nc pack_l_0 pblast_l rxchn2_4 gnd pack_l_1 rxchn_2_3 pdata_0 rxchn_2_2 gnd preq_l_0 rxchn_2_1 pdata_1 rxchn_2_0 vdd preq_l_1 pdata_2 pint_l pdata_3 gnd pclk pdata_4 ptype_0 pdata_5 vdd ptype_1 pdata_6 ptype_2 pdata_7 gnd pdack_l paddr_0 pdben_l paddr_1 vdd pas_l paddr_2 pcs_l rxchn_1_0 gnd paddr_3 rxchn_1_1 prd_l rxchn_1_2 paddr_4 gnd rxchn_1_3 pwr_l rxchn_1_4 paddr_5 nc nc nc txchclk_0 txohclk_0 rxchn_0_0 txoh_0 rxchn_0_1 txmsync_0 rxchn_0_2 txsync_0 rxchn_0_3 gnd txserclk_0 rxchn_0_4 txser_0 rxlos_0 rxohclk_0 rxoh_0 rxchclk_0 rxcasmsync_0 vdd rxcrcmsync_0 rxsync_0 rxserclk_0 rxser_0 oscclk reset_l 8khzref testmode gnd txser_1 txserclk_1 txsync_1 txmsync_1 txoh_1 txohclk_1 rxser_1 txchclk_1 rxserclk_1 vdd rxsync_1 txchn_1_4 rxcrcmsync_1 txchn_1_3 rxcasmsync_1 rxchclk_1 txchn_1_2 rxoh_1 txchn_1_1 gnd rxohclk_1 txchn_1_0 rxlos_1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 208 lead pqfp p art n umber p ackage o perating t emperature r ange XRT84V24iv-208 208 lead pqfp -40 c to +85 c XRT84V24iv-160 160 lead pqfp -40 c to +85 c
XRT84V24 quad e1 framer ic preliminary rev. 1.0.1 4 package dimensions
quad e1 framer ic XRT84V24 preliminary rev. 1.0.1 5
XRT84V24 quad e1 framer ic preliminary rev. 1.0.1 6 notice exar corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. exar corporation assumes no responsibility for the use of any cir- cuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. charts and schedules contained here in are only for illustration pur- poses and may vary depending upon a users specific application. while the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. exar corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. products are not authorized for use in such applications unless exar corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of exar corporation is adequately protected under the circumstances. copyright 1999 exar corporation datasheet october 1999 reproduction, in part or whole, without the prior written consent of exar corporation is prohibited. revision history
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